library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- This module implemnts a muxer with generic input and output
entity muxer is
generic (N : integer := 32);
port (	data_0	: in   std_logic_vector (N-1 downto 0);
		data_1	: in   std_logic_vector (N-1 downto 0);
		sel 		: in   std_logic;
		output	: out std_logic_vector (N-1 downto 0)
);
end muxer;

architecture Structural of muxer is
component mux21 is
port (	A : in   std_logic;
		B : in   std_logic;
		S : in   std_logic;
		O : out std_logic
);
end component;

begin

gen: for i in 0 to N-1 generate 
	mux_n: mux21 port
	map (	A => data_0(i),
			B => data_1(i),
			S => sel,
			O => output(i)      
   );
end generate;

end Structural;
